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Samsung's Processing-in-Memory (PIM)
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- DeepHorus
Samsung has unveiled a major advancement in in-memory computing with its LPDDR5X-PIM (Processing-in-Memory) technology, detailed at the Hot Chips 2026 conference. The company is embedding compute units directly into its memory chips to overcome a fundamental bottleneck in conventional computer architecture. This approach promises to dramatically increase bandwidth and efficiency for data-intensive tasks like artificial intelligence.
The core issue Samsung addresses is the limitation of traditional DRAM access. While a memory chip contains many internal banks with high bandwidth, the external interface to the main processor acts as a chokepoint. A standard memory controller can only access a fraction of the available internal bandwidth at once, creating latency and power inefficiencies as data must constantly move back and forth.
Samsung's solution integrates a Processing-in-Memory (PIM) block into each of the 16 banks within an LPDDR5X-9600 chip. Each PIM block contains a multiply-accumulate (MAC) array, enabling computation directly where the data resides. Theoretically, this architecture unlocks a massive internal bandwidth of 614 GB/s across all banks, compared to just 76.8 GB/s for conventional dual-bank access.
The compute capability, while modest per chip, is designed to scale. A single LPDDR5X-PIM chip can sustain 0.3 INT8 TOPS. However, in an eight-chip configuration, the total throughput reaches 9.6 INT8 TOPS. This aggregate performance approaches that of some dedicated Neural Processing Units (NPUs), such as the one found in Intel's Meteor Lake processors, but with integrated high-capacity memory.
A key innovation is maintaining compatibility with standard LPDDR5X protocols. Samsung uses special row addresses to switch the memory controller into a multi-bank mode that broadcasts commands to all PIM blocks simultaneously. This allows software to load model weights into standard DRAM, then switch modes to perform parallel computation across all memory banks.
Industry analysts view this as a significant step for AI inference at the edge, where power and memory bandwidth are critical constraints. The technology could enable more powerful AI models to run efficiently on devices without relying on separate, power-hungry accelerators. However, the cost of deploying systems with multiple high-density memory modules remains a consideration.
Samsung's presentation at Hot Chips signals a continued commitment to commercializing in-memory compute. The next steps will involve refining the architecture for higher precision and greater compute density. If successful, LPDDR5X-PIM could become a foundational component in future low-power AI hardware, blending memory and processing into a single, efficient package.
