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Leveraging FeRAM and 3D Stacking to Break the AI Memory Bottleneck
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- DeepHorus
Chip startup Kepler Computing officially announced its debut on September 10 local time. The company was founded in 2018, and its goal is directly aimed at the increasingly severe bottlenecks in memory energy consumption and bandwidth, as well as production capacity and cost, in the AI semiconductor field. IT Home reported on September 14 that Kepler Computing claims its memory solution has bandwidth close to SRAM, capacity superior to SRAM and even HBM, and does not require EUV lithography equipment.
Currently, the AI semiconductor field is facing multiple bottlenecks in memory energy consumption and bandwidth, as well as production capacity and cost. Kepler Computing claims that its solution can provide memory with bandwidth close to SRAM and capacity superior to SRAM and even HBM. This makes it one of the new players attempting to break through the memory wall.
According to the introduction, this solution uses 3D stacked integration technology and should belong to FeRAM (ferroelectric memory). This solution does not require EUV lithography equipment. The company says its bandwidth is close to SRAM and its capacity is superior to SRAM and even HBM, and it is expected to achieve a balance between speed and capacity.
In terms of timeline, Kepler Computing plans to produce samples by the end of 2026 and expand production capacity in 2027. This means there is still some time before its technology reaches commercial validation. The company hopes that by then it can prove the competitiveness of its memory solution in the AI field.
On the manufacturing side, Kepler Computing is using GlobalFoundries' 28nm capacity in Singapore for trial production. The company also stated that it will also manufacture in the United States in the future. It claims that retrofitting an existing wafer fab for innovative memory production took only 8 months, one-third of the usual time.
If this solution can be realized, the memory bottleneck in the AI semiconductor field is expected to be alleviated. Not requiring EUV lithography equipment also means that more existing wafer fabs may participate in production, thereby improving capacity and cost pressures. However, its actual performance still remains to be verified later.
Looking ahead, Kepler Computing plans to use material innovation to break through the inherent limitations of existing CMOS (complementary metal-oxide-semiconductor). The company hopes to improve chips' energy efficiency and enhance production capacity through lower voltages. Whether this roadmap can be delivered will depend on its actual progress after producing samples at the end of 2026.
