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Reverse-engineering the Intel 8087's tangent algorithm: more than CORDIC
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A detailed reverse-engineering investigation into Intel’s 8087 floating-point coprocessor has revealed the design behind its FPTAN instruction, showing that the chip did more than run a textbook CORDIC loop. Introduced in 1980, the 8087 brought hardware-assisted, 80-bit extended-precision arithmetic to the IBM PC and other 8086-based systems, transforming the practical performance of scientific and engineering software. Its tangent operation became a striking example of Intel’s ability to combine specialized circuits, constants, and microcode. Yet decoding the die indicates that the algorithm was a carefully tuned hybrid rather than a single textbook method.
The analysis began with a physical examination of an 8087 chip. After removing the package, the researcher created a high-resolution image of the die with a microscope and mapped its major functional blocks. A large rectangular area in the center contained the control ROM, which held 1,648 micro-instructions governing the coprocessor’s internal operations. The lower half of the chip contained the datapath, including circuitry for manipulating the processor’s 80-bit floating-point values. This combination of visible hardware and stored instructions made it possible to reconstruct not merely what the chip calculated, but how it coordinated the calculation.
CORDIC, or Coordinate Rotation Digital Computer, was already well suited to the limited hardware of the 1950s. Jack Volder developed the technique in 1956 while working on a digital navigation computer for the B-58 Hustler, a bomber capable of flying at Mach 2. Unlike an analog resolver, a digital system of that era struggled to produce sine and cosine values quickly and accurately. CORDIC addressed the problem by representing an angle as a sequence of special rotations whose tangents were simple powers of two. A compact table supplied the rotation angles, allowing hardware to use shifts and additions instead of costly multipliers.
The 8087 implementation reflects the algorithm’s essential components. Its constant ROM stores the CORDIC angles and scaling factors, while a 16-bit shift register tracks which direction each iteration should rotate. A large shifter moves the active 64-bit portion of a floating-point value, and a general-purpose adder performs each shift-and-add step. The B and sum registers feed results through the arithmetic path, while eight stack registers and temporary registers preserve operands and intermediate coordinates. Intel therefore reused the same relatively compact arithmetic hardware for trigonometric functions, multiplication, division, and square-root operations.
Although CORDIC supplied the core rotation process, the decoded tangent routine also relied on polynomial approximation. Polynomial stages helped reduce or refine the input before or during the iterative calculation, allowing Intel to balance speed against precision. This division of labor was more effective than depending exclusively on either CORDIC or a conventional polynomial scheme. CORDIC delivered rapid convergence with simple shift-and-add operations, while the polynomial component addressed range reduction and accuracy requirements. The result was a machine-specific design optimized around the 8087’s constants, status bits, registers, and microinstruction sequence.
The performance gains were substantial for contemporary systems. On an 8086 system without the coprocessor, a software tangent calculation could require approximately 13,000 microseconds, while the 8087 completed the operation in about 90 microseconds. That represented a speedup of roughly 140 times and made interactive trigonometric calculations far more practical. More importantly, the coprocessor offloaded numerically intensive work from the main processor, allowing software to maintain greater precision without imposing the same severe timing penalty. The FPTAN instruction consequently became a key demonstration of the value of dedicated floating-point hardware.
The finding strengthens the 8087’s historical reputation while complicating a common simplified account of its design. Rather than presenting the chip as a direct implementation of one elegant algorithm, the reverse-engineering exposes a layered engineering approach in which tables, iteration, polynomial approximation, and specialized data paths work together. For hardware historians, the result reinforces the importance of studying microcode alongside transistors because either layer alone would not explain the full tangent algorithm. Future FPGA implementations, emulator authors, and retro-computing enthusiasts can use the reconstruction to improve cycle-accurate models and understand the compromises behind original hardware. It also offers a broader lesson: historically important computing systems often achieve their speed not from a single breakthrough, but from tightly integrating several methods around the strengths of the machine.
