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Cerebras Deploys Trillion-Parameter AI Models
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- DeepHorus
Cerebras has outlined a method for deploying trillion-parameter AI models across its wafer-scale chips, showing how a 3-trillion-parameter model can run at 1,000-2,000+ tokens per second. The company detailed the approach using the open-source Kimi K3 model. It marks a step toward serving frontier-scale AI on specialized hardware.
A single Cerebras WSE-3 wafer carries 44 GB of on-chip memory, but trillion-parameter models require terabytes for their weights alone. Cerebras therefore splits large models across multiple wafers rather than fitting them on one chip. The design keeps model layers resident on-chip and passes only activations between wafers.
Kimi K3 has about 3 trillion parameters across 69 linear-attention layers and 24 dense layers. Using 4-bit weight quantization, its weights total roughly 1.5 terabytes, or about 16 GB per layer. Cerebras places one dense layer per wafer to leave room for an 8-bit KV cache and two linear layers per wafer.
That layout requires 35 wafers for the linear layers and 24 for the dense layers, for 59 WSE-3 wafers in total. The wafers are connected in a pipeline, with activations moving between stages via RDMA over Ethernet at roughly 2 microseconds per hop. Because each layer fits on-chip, model weights stay put.
The approach allows a single request to flow through the wafer pipeline like an assembly line, with each stage producing intermediate results for the next. Cerebras says this design supports 256k-token average requests and high concurrency, not batch size one. That matters because long-context inference demands both memory capacity and low latency.
Kimi K3 scores 88.3% on Terminal-Bench 2.1, close to GPT-5.6 Sol's 88.8%, and 91.2% on BrowseComp versus 90.4%. Those results suggest open models can reach frontier-level coding and agentic performance. Cerebras' deployment shows such models can be served without moving weights off-chip.
The method points to a scalable path for multi-trillion-parameter inference on wafer-scale hardware. As models grow, Cerebras argues that keeping entire layers in on-chip SRAM will become more important. The company expects the pipeline design to sustain high throughput for concurrent requests.
